module c6502_decode(
    //addr,
    dat,
    clk_in,

,base_jmprel
,base_alu
,base_shift
,base_flg_set
,is_cmp
,storeA
,storeX
,storeY
,loadA
,loadX
,loadY
,do_zp
,do_zpx
,do_abs
,do_abx
,do_aby
);
    input wire clk_in;
    input wire[7:0] dat;

    /*
    tya是格格不入的指令
        dey使用的字节88应该换成tya

    dex应该换成=>'hea,dey=>'hca
    nop=>98
    */

    output wire base_flg_set; assign base_flg_set   = (dat[4:0]=='h18);
    output wire base_jmprel ; assign base_jmprel    = (dat[4:0]=='h10);
    output wire base_alu    ; assign base_alu       = (dat[1:0]=='d1);
    output wire base_shift  ; assign base_shift     = (dat[1:0]=='d2)&~dat[7];

    /* output */ wire is_store    ; assign is_store       = (dat[7:5]=='d4);
    /* output */ wire is_load     ; assign is_load        = (dat[7:5]=='d5);

    output wire loadA       ; assign loadA          = is_load&(dat[1:0]=='d1)&(dat[7]);
    output wire loadX       ; assign loadX          = is_load&(dat[1:0]=='d2)&(dat[7]);
    output wire loadY       ; assign loadY          = is_load&(dat[1:0]=='d0)&(dat[7]);

    output wire storeA      ; assign storeA          = is_store&(dat[1:0]=='d1)&(dat[7]);
    output wire storeX      ; assign storeX          = is_store&(dat[1:0]=='d2)&(dat[7]);
    output wire storeY      ; assign storeY          = is_store&(dat[1:0]=='d0)&(dat[7]);

    output wire is_cmp      ; assign is_cmp         = (dat[7:5]=='d6)|(dat[7:5]=='d7);

    wire do_indx     ; assign do_indx = (dat[4:2]=='b000)&(dat[0]);
    wire do_indy     ; assign do_indy = (dat[4:2]=='b100)&(dat[0]);
    output wire do_zp       ; assign do_zp   = (dat[4:2]=='b001)|do_indx|do_indy;
    output wire do_zpx      ; assign do_zpx  = (dat[4:2]=='b101)|do_indx;
    output wire do_abs      ; assign do_abs  = (dat[4:2]=='b011)|do_indx|do_indy;
    output wire do_abx      ; assign do_abx  = (dat[4:2]=='b110);
    output wire do_aby      ; assign do_aby  = ((dat[4:2]=='b111)&(dat[0]))|do_indy;

endmodule


module c6502(
    addr,
    dat,
    clk_in,
    rst_n,
    irq,
    nmi,
    rw
);
    input wire clk_in;
    inout wire[7:0] dat;
    input wire rst_n;
    output wire[15:0] addr;
    output wire rw;     reg rw_reg = 'b1; assign rw = rw_reg;
    input wire irq;
    input wire nmi;

    c6502_decode decode(
    dat,
 clk_in,
,base_jmprel
,base_alu
,base_shift
,base_flg_set
,is_cmp
,storeA
,storeX
,storeY
,loadA
,loadX
,loadY
,do_zp
,do_zpx
,do_abs
,do_abx
,do_aby
    );
/*
使用组合电路来实现

ld指令与锁存处理
    M   \
    S    >-->(A,Y,X)
    X   /

    LDA -> M->A
    TXA -> X->A
    TYA -> Y->A

    LDX -> M->X
    TAX -> A->X
    TSX -> S->X

    LDY -> M->Y
    TAY -> A->Y

    如LDA,TXA,TYA的实现时序应该实现如下.
        AA为A寄存器的数值.  BB为X寄存器的数值. CC为Y寄存器的数值,DD为立即数数据,SRC为源数据
        DAT为数据线数据

    CLK     ^^^^____^^^^____^^^^____^^^^____^^^^____
    TXA     |BB |BB |BB |BB |指令结束
    TYA     |BB |BB |CC |CC |指令结束
    LDA     |BB |BB |BB |DD |指令结束
    DAT(lda)|A9 |A9 |DD |DD |
    DAT(TXA)|8a |8a |DD |DD |
    srcX   _^^^_____________________    数据是从X寄存器来
    srcY    ________^^^_____________    数据是从y寄存器来
    srcD    ____________^^^_________    数据是从存储设备来

    其实可以如下实现(lda指令如下实现), A表示A寄存器
                            |结束
    A(lda)  |BB |CC |CC |CC |DD
    A(txa)  |BB |BB |BB |BB |BB
    A(tya)  |BB |CC |CC |CC |CC

*/




endmodule
